1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a method of driving a shift register, a gate driver, and a display device having the same with greater reliability.
2. Discussion of the Related Art
A display device for displaying an image by controlling the pixels arranged in a matrix has been widely used. Examples of the display devices are a liquid crystal display (LCD) device, an organic light emitting diode (OLED) device, etc. Such a display device includes a display panel having the pixels arranged in a matrix, a gate driver for scanning pixels line by line, and a data driver for supplying an image data.
Recently, a display device having a gate driver and/or a data driver embedded on a display panel has been actively developed to achieve simplified fabricating process, light weight and slim size. In addition, such an embedded display panel can reduce manufacturing cost. When manufacturing the display panel, the gate diver and/or the data driver can be manufactured at the same time. That is, when a plurality of thin film transistors (TFTs) are manufactured, the gate driver and/or the data driver can be manufactured through the identical semiconductor processes used in the TFT. Each of the drivers includes a plurality of shift registers for outputting signals. For example, when the display panel has ten gate lines, ten shift registers are provided to supply their signals to the ten gate lines, respectively.
FIG. 1 is a block diagram of a related art gate driver. Referring to FIG. 1, the related art gate driver includes a plurality of shift registers SRC1 to SRC[N+1] connected in a cascaded manner. An output terminal OUT of each shift register is connected to a set terminal SET of the next shift register. The shift registers include n number of shift registers SRC1 to SRC[N] corresponding to n number of gate lines, and a dummy shift register SRC[N+1] for resetting the last shift register SRC[N].
The first shift register SRC1 is set by a pulse start signal STV. The pulse start signal is a pulse synchronized with a vertical synchronizing signal Vsync. Each of the shift registers SR2 to SRC[N+1] is set by an output signal of its previous shift register. When there are n number of the gate lines, signals GOUT1 to GOUT[N] of the shift registers are connected to the corresponding gate lines, and an output signal GOUT[N+1] of the dummy shift register SRC[N+1] is not connected to any gate line.
A first clock CKV is supplied to the odd-numbered shift registers SRC1, SRC3, etc., and a second clock CKVB is supplied to the even-numbered shift registers SRC2, SRC4 etc. Here, a phase of the first clock CKV is opposite to that of the second clock CKVB. The first clock CKV is simultaneously applied to the odd-numbered shift registers SRC1, SRC3, etc., and the second clock CKVB is simultaneously applied to the even-numbered shift registers SRC2, SRC4, etc.
The timing when a pulse start signal STV is applied to the first shift register SRC1 is when the second clock CKVB is high. The shift registers SRC1 to SRC[N] output the respective signals GOUT1 to GOUT[N] in synchronization with the first clock CKV and the second clock CKVB. And, each of the shift registers SRC1 to SRC[N] except the dummy shift register SRC[N+1] is reset by the output signal of its subsequent shift register.
As explained above, each of the shift registers SRC1 to SRC[N] produces the output signal in synchronization with the first and second clocks CKV and CKVB. And, each shift register SRC1 to SRC[N] is set by the output signal of its previous shift register. The reset signal is the output signal of subsequent shift register to the current one which is provided to corresponding shift register SRC1 to SRC[N]. However, since there is no shift register provided next to the dummy shift register SRC[N+1], the dummy shift register SRC[N+1] is reset by its own output signal GOUT[N+1].
FIG. 2 is a circuit diagram of a first shift register illustrated in FIG. 1. FIG. 3 is a waveform diagram of multiple signals for driving the first shift register of FIG. 2. Since the shift registers illustrated in FIG. 1 have the identical structure to one another, only the first shift register SRC1 will be described for convenience.
When the pulse start signal STV is high, the first clock CKV is low and the second clock CKVB is high. Referring to FIGS. 2 and 3, the first shift register SRC1 is set by the pulse start signal STV of a high state during a second clock (CKVB) period. That is, when the pulse start signal STV is applied, a Q node is charged to a voltage of the pulse start signal STV. A first transistor M1 is turned on by the charged Q node. Then, a QB node is discharged by a voltage difference (VDD−VSS) between a first power supply voltage and a second power supply voltage. Consequently, a low voltage is maintained by a ratio of a resistance R1 of a first transistor M1 to a resistance R6 of a sixth transistor M6.
Then during a subsequent clock period when a first clock CKV is high, a first output signal GOUT1 is output in response to the first clock CKV. That is, when the first clock CKV is applied to the second transistor M2, a bootstrapping is caused by a drain-gate capacitance Cgd in a second transistor M2, and thus, the Q node is charged with a voltage higher than that of the charged pulse start signal STV. Accordingly, the second transistor M2 is turned on, and thus, the first clock CKV is output as the first output signal GOUT1.
During the next clock period when the second clock (CKVB) is high, the first shift register SRC1 is reset by the second output signal GOUT2 of its subsequent shift register SRC2. That is, when a fifth transistor M5 is turned on by the second output signal GOUT2 of the shift register SRC2, the Q node is discharged by a first power supply voltage VSS passing through the fifth transistor M5. Additionally, the first transistor M1 is turned off by the discharged Q node, and the QB node is charged with the second supply voltage VDD passing through the sixth transistor M6, so that third and fourth transistors M3 and M4 are turned on by the charged QB node. Accordingly, the Q node is easily discharged by the first supply voltage VSS passing through the turned-on fourth transistor M4. In this case, most of the output signal GOUT1 is discharged through a source-drain path of the second transistor M2, and the remaining output signal GOUT1 is discharged through the first power supply voltage VSS by the turned-on third transistor M3.
Since the other shift registers SRC2 to SRC[N] operate in the same way as the first shift register SRC1, the signals GOUT1 to GOUT[N] of a high state are output sequentially. The signals GOUT1 to GOUT[N] of a high state are sequentially output during one frame by the shift registers SRC1 to SRC[N]. Then, these processes are repeated frame by frame. However, when the first shift register SRC1 is reset by the second output signal GOUT2 of the second shift register SRC2, the first output signal GOUT1 of the first shift register SRC1 is not discharged easily to a low state.
Generally, the first output signal of a high state is more easily discharged to a low state through the second transistor M2 rather than the third transistor M3. However, since the second transistor M2 is in the turned-off state, it is difficult to discharge the first output signal GOUT1 through the second transistor M2. Thus, the first output signal GOUT1 cannot be discharged quickly. As mentioned earlier, the first output signal GOUT1 is supplied to a first gate line connected to a pixel. When the first output signal Gout1 can not be discharged easily, then the thin film transistor (TFT) provided on the pixel cannot be turned off. Therefore, when a TFT connected to a second gate line is turned on by the second output signal GOUT2 supplied to the second gate line, a data signal supplied to the pixel connected to the second gate line is also supplied to the pixel connected to the first gate line. Consequently, the signals are not discharged fast enough to display an image properly, causing image deterioration.
FIG. 4 is a graph showing the output signal falling time in the shift register provided for the related art gate driver of FIG. 1, which is superimposed with a single clock period. As described above, an output signal of a high state has to be discharged to become the output signal of a low state within the single clock period. However, as shown in FIG. 4, the output signal cannot be completely discharged to a low state at a time when the single clock period is finished.
Referring to FIG. 2, the Q node is reset by the second output signal GOUT2 of the second shift register SRC2. Since the second transistor M2 connected to the Q node is turned off, the first output signal GOUT1 of a high state is not discharged rapidly. Thus, the first output signal GOUT1 of the first shift register SRC1 overlaps an output signal of another shift register (e.g. a second shift register SRC2). Accordingly, it is difficult to control the signals accurately. When the signals are supplied to the LCD, an identical image is displayed on adjacent gate lines and therefore the image failure is caused.